The present invention relates to a semiconductor device and a manufacturing method thereof, and can be preferably used in a semiconductor device having, for example, an LDMOSFET.
A semiconductor device having an LDMOSFET (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor: hereinafter, referred to as a “lateral MOS transistor”) is one of those for electric power for which high pressure resistance is required. For example, in a semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2006-108208, an electric field control electrode is formed on a part of a field oxide film located between a gate electrode and a drain electrode. A voltage controlled independently from the gate electrode is applied to the electric field control electrode. An electron accumulation layer is formed at the interface between the field oxide film and an N-well diffusion layer by applying a high voltage to the electric field control electrode. Accordingly, ON-resistance can be reduced.
Further, in a semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2014-107302, a p-type drift region and an insulating region are formed between a channel formation region and a drain region. A gate electrode is formed so as to extend from the channel formation region to the insulating region by interposing a gate insulating film while having an opening exposing the interface part between the channel formation region and the insulating region, and the reliability of the gate insulating film can be improved by forming the opening at the gate electrode.
Further, in a semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2009-278100, an orthogonal gate electrode having a gate electrode folded into an STI (Shallow Trench Isolation) oxide film region is formed. The orthogonal gate electrode reduces a capacity overlapped between a gate and a drain, and the switching time can be made faster.